Semiconductor Engineering

Heterogeneous NPU Data Movement: What The Execution Flow Shows

Heterogeneous NPU designs bring together multiple specialized compute engines to support the range of operators required by ...
GitHub

Systolic-Processor-Architecture /DPU_array_matrix_multiplication_3

DPU0: DPU_matrix_multiplication port map(A0,B0,CLK,clear,S03,S01,O0); DPU1: DPU_matrix_multiplication port map(A1,S01,CLK,clear,S14,S12,O1); DPU2: DPU_matrix ...
IEEE

Energy Efficient Exact and Approximate Systolic Array Architecture for Matrix Multiplication

Abstract: Deep Neural Networks (DNNs) require highly efficient matrix multiplication engines for complex computations. This paper presents a Systolic Array (SA) architecture incorporating novel exact ...
IEEE

MIRAGE: Micro-Ring-Assisted General Engine with Phase-Error Compensation for Scalable Full-Range Matrix-Vector Multiplication

Abstract: Matrix-vector multiplication (MVM) underpins modern AI workloads, yet scaling it on electronic hardware is increasingly constrained by energy, bandwidth, and latency bottlenecks. Photonic ...
GitHub

CLAUDE.md

Read the paper — Full technical details, 90+ experiments, and the story of how an AI and a human built this in 24 hours. Pure C/Metal inference engine that runs Qwen3.5-397B-A17B (a 397 billion ...